1. Field of the Invention
The invention relates to computer memory systems in general and more particularly to high speed semiconductor memories.
2. Prior Art
The designers of all forms and classes of computer systems have commonly expressed the desire to provide higher speed systems at relatively low cost. A typical computer system has at least one central processing unit (CPU) which is connected to a memory subsystem over a system bus. If designers are going to be successful in meeting a satisfactory speed/cost goal, improvements are required not only in the CPU section of the computer systems but also in the memory sub-system.
Computer memories can be broadly classified into three classes, namely: dynamic random access memory (DRAM), static random access memory (SRAM) and hybrid memory. Even though the three types of memories are fabricated from semiconductor devices, there are certain advantages and disadvantages associated with each type. Therefore, if one wishes to provide an optimum memory assembly, one has to overcome the disadvantages that are associated with a particular type of memory.
DRAMs have been widely used in the computer industry. This type of memory is attractive because of its high density and low power consumption. Because of the high density and low power consumption, DRAMs are low cost memories which are used whenever large memory capacity is required. The drawback with this type of memory is that the stored data volatilizes in a relatively short time period, if not refreshed. Therefore, the DRAM must be refreshed at given time intervals (usually every 2 m secs). The refreshing procedure requires a circuit which generates a refresh or an address request signal for refreshing a selected memory zone and a refresh control signal to control the cycle timing of the read and write operation of data with the refreshing operation. In addition, a multiplexor for selecting either an address for refreshing or an address for a read and write operation within the cycle timing may also be required.
On the other hand, the SRAM is lower density and consumes a relatively large amount of power. As a result, it is usually expensive and is used for relatively small capacity memories. In spite of its drawback, the SRAM requires no refreshing cycle and thus no additional refresh circuitry is required. In addition, the SRAM is an inherently faster device than the DRAM.
In an attempt to circumvent the above-described shortcomings and at the same time provide a memory system with acceptable speed/cost characteristics, the prior art has developed hybrid memory systems. A typical hybrid memory system consists of a combination of DRAMs, SRAMs and memory controllers. In the hybrid configuration the SRAM functions as a distributed cache memory which is fabricated on the DRAM module or on a separate module.
An example of a prior art hybrid memory is disclosed in U.S. Pat. No. 4,725,945 issued to Kronstadt et al. FIG. 1, of this patent, discloses a prior art microcomputer system in which an instruction and/or data cache is fabricated on the CPU side of the system bus. The cache is a separate SRAM module interconnected via the bus to the DRAMs. The control logic associated with the cache attempts to maximize the number of accesses (called hits) to the cache and minimizes the number of accesses to the DRAMs. Because the access time for the cache is much shorter than the access time for the DRAMs, system throughput can be increased if the instruction and/or data. to be used in a particular operation is in the cache rather than in the DRAM. One of the problems associated with the displaced or separate storage cache is that a relatively large number of pins are needed on the SRAM module and the DRAMs for interconnection purposes.
FIGS. 2-6 of the Kronstadt et al patent disclose a hybrid memory which is an improvement over the memory of FIG. 1. The improved hybrid memory includes a plurality of memory banks. Each bank consists of an array of DRAMs and an on-chip SRAM buffer for storing an entire row of DRAM data. A memory controller receives real addresses on the memory bus and extracts bank and row numbers from the address. The memory controller determines whether the access row for a memory bank is in the distributed cache for the bank. Even though this system works well for its intended purpose, it has one drawback in that if a "miss" occurs the contents of the cache are replaced with the data which is read out from the DRAMs. A "miss" occurs if a requested piece of information is not present in the cache. Replacing the contents of the cache on the occurrence of a miss tends to reduce system throughput. This adverse effect is more pronounced in systems where instructions and data are stored in the same memory. Usually, several instructions are stored in the cache buffer and are used repeatedly albeit with different data. Because the design requires replacing the data whenever a "miss" occurs, instructions which are used repeatedly are often destroyed and have to be replaced from the DRAM array. This negates the benefits that the SRAM usually provides.
Another type of prior art hybrid memory is the Video RAM. In the video RAM a serial read (SRAM) register has been added to a DRAM array. Once loaded, this register can be accessed through its serial read port. This type of memory is not well suited for use as computer memories because data can only be extracted serially from the SRAM. An example of the prior art video RAM is set forth in U.S. Pat. No. 4,731,758 to Heng-Mun Lam et al.
Still other types of hybrid memories with complicated structures are set forth in U.S. Pat. Nos. 4,417,318, 4,589,067, 4,608,666 and 4,758,987. Probably, the least attractive features of these memories are their complex structures.